High Performance Digital Pulsewidth-Control Circuit With Programmable Duty Cycle

In High speed operations the duty cycle of the clock signal is to bé calibrated at 50%. But the variations in process, voltage and temperature (PVT) influences the duty cycle and make it difficult to calibrate the duty cycle at 50%. To overcome this deviation Pulse width control loops (PWCLs) are used. This work presents a high performance and fast locking all digital pulse width control circuit with programmable duty cycle. For the pulse width control circuit, two delay lines and a time to digital detector is used which reduces the amount of hardware required in the circuit. The output duty cycle is calculated with the help of a new duty cycle setting circuit without the need for a look-up table. The new design is developed in Hardware description language (HDL) to improve the design effort. The pulsewidth-control circuit is capable of operating over a wide frequency range with fewer delay cells. The reliability of the circuit is increased by using a TMR system. Experimental results show that the proposed approach is consuming less area and power when compared with the previous methods and the circuit is reliable.